We have 6 members working on designing the main flight computer, sensing, apogee detection, onboard recovery system, the battery management system, and the electro-mechanical integration of the electronic hardware spatially inside of the rocket. We have fabricated and tested the main flight computer which has a microcontroller board, a long-range radio module, an altimeter, an accelerometer, and a GPS measurement unit all working together to track in-flight motion.
We have one PCB module with integrated data logging, GPS, altimeter, accelerometer, radio via breakout boards and hope to eventually move to a fully surface mounted solution. We also hope to include additional componenets in the future such as a camera.
Our rocket will be powered by a double redundant lithium-ion battery pack. We are also implementing circuitry for sending battery telemetry information to the main ground station.
Once the rocket reaches apogee (10,000 feet), the Avionics system will power an electrical ignitor which will be used to separate the rocket and deploy the drogue parachute.
Out telemetry module uses a 900mhz long radio to transmit flight data back down the the ground in real time. The data can be visualized (and logged) on our custom ground station software.
From its initial launch position on the pad to its final destination after launch, all systems of the avionics subteam must be able to interface with the main computer. The main computer has two primary jobs during the flight of the rocket. Foremost, the computer will interface with the sensing module to take in the information necessary to determine when to interface with the recovery module. Throughout the flight, it will also pass on necessary flight information to the ground station every second (including GPS coordinates, readouts from the sensing board, and all battery & arming information), while also writing to an onboard “blackbox” to validate the flight data.
For the distant future of rocketry, we are pushing for learning basic semiconductor design for application specific integrated circuits (ASICs). We are working towards creating our own standard cell library with low-level very-large-scale integration (VLSI) layouts for representing various logic gates. This would make it possible for future designers to focus on the high-level (logical function) aspect of digital design. In the industry, standard cell methodology has helped designers scale ASICs from comparatively simple single-function ICs (of several thousand gates), to complex multi-million gate system-on-a-chip (SoC) devices.